Publications of Schemmel, J.
Select a view.18 publication entries, 5 of them (printed in bold in the list) acknowledge the project support.
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Conference contribution: poster
Paper (reviewed)
| Bill et al. 2010 | Bill, J., Schuch, K., Brüderle, D., Schemmel, J., Maass, W. and Meier, K. | Compensating inhomogeneities of neuromorphic VLSI devices via short-term synaptic plasticity | Front. Comput. Neurosci. (2010) 4:129. doi:10.3389/fncom.2010.00129 |
abstract, BibTeX |
| Brüderle et al. 2009 | Brüderle, D., Müller, E., Davison, A., Muller, E., Schemmel, J. and Meier, K. | Establishing a novel modeling tool: A Python-based interface for a neuromorphic hardware system | Front. Neuroinform. (2009) 3:17 doi:10.3389/neuro.11.017.2009 |
abstract, fulltext, BibTeX |
| Bruederle et al. 2011 | Brüderle, D., Petrovici, M.A., Vogginger, B., Ehrlich, M., Pfeil, T., Millner, S., Grübl, A., Wendt, K., Müller, E., Schwartz, M.O., de Oliveira, D.H., Jeltsch, S., Fieres, J., Schilling, M., Müller, P., Breitwieser, O., Petkov, V., Muller, L., Davison, A.P., Krishnamurthy, P., Kremkow, J., Lundqvist, M., Muller, E., Partzsch, J., Scholze, S., Zühl, L., Mayr, C., Destexhe, A., Diesmann, M., Potjans, T.C., Lansner, A., Schüffny, R., Schemmel, J. and Meier, K. | A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems. | Biol Cybern. (2011) 104(4-5):263-96 doi:10.1007/s00422-011-0435-9 |
fulltext, BibTeX |
| Indiveri et al. | Indiveri, G., Linares-Barranco, B., Hamilton, T. J., van Schaik, A., Etienne-Cummings, R., Delbruck, T., Liu, S.-C., Dudek, P., Häfliger, P., Renaud, S., Schemmel, J., Cauwenberghs, G., Arthur, J., Hynna, K., Folowosele, F., Saïghi, S., Serrano-Gotarredona, T., Wijekoon, J., Wang, Y. and Boahen, K. | Neuromorphic silicon neuron circuits | Front. Neurosci. (2011) 5:73 doi:10.3389/fnins.2011.00073 |
fulltext, BibTeX |
| Schemmel et al. 2008a | Schemmel, J., Fieres, J. and Meier, K. | Realizing Biological Spiking Network Models in a Configurable Wafer-Scale Hardware System | IEEE International Joint Conference on Neural Networks IJCNN (2008) : 969-976 doi:10.1109/IJCNN.2008.4633916 |
abstract, BibTeX |
| Schemmel et al. 2008b | Schemmel, J., Fieres, J. and Meier, K. | Wafer-Scale Integration of Analog Neural Networks | IEEE International Joint Conference on Neural Networks IJCNN (2008) : 431-438 doi:10.1109/IJCNN.2008.4633828 |
fulltext, BibTeX |
Conference contribution: poster
| Bruederle et al. 2007 | Bruederle, D., Gruebl, A., Meier, K., Mueller, E. and Schemmel, J. | A Software Framework for Tuning the Dynamics of Neuromorphic Silicon Towards Biology | n Proc. of IWANN 2007, San Sebastián, Spain, June 2007, Springer LNCS 4507, pp. 479 - 486 | abstract, fulltext |
| Brüderle et al. 2009c | Brüderle, D., Kremkow, J., Bauer, A., Perrinet, L.U., Aertsen, A., Masson, G.S., Meier, K. and Schemmel, J. | Matching Network Dynamics Generated by a Neuromorphic Hardware System and by a Software Simulator | Bernstein Conference on Computational Neurosciences (2009) | |
| Bruederle et al. 2010 | Brüderle, D., Bill, J., Kaplan, B., Kremkow, J., Meier, K., Müller, E. and Schemmel, J. | Simulator-like exploration of cortical network architectures with a mixed-signal VLSI system | Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS) (2010): 2784-2787 doi:10.1109/ISCAS.2010.5537005 |
fulltext |
| Ehrlich et al. 2007 | Ehrlich, M., Mayr, C., Eisenreich, H., Henker, S., Srowig, A., Gruebl, A., Schemmel, J. and Schüffny, R. | Wafer-scale VLSI implementations of pulse coupled neural networks | International Conference on Sensors, Circuits and Instrumentation Systems (SSD-07), Hammamet-Tunisia 2007, p. 409 ff., electronic publication. | fulltext |
| Fieres et al. 2006 | Fieres, J., Schemmel, J. and Meier, K. | Training convolutional networks of threshold neurons suited for low-power hardware implementation | Proceedings of the 2006 International Joint Conference on Neural Networks (IJCNN 2006), 21--28, IEEE Press (2006) | abstract, fulltext |
| Fieres et al. 2006b | Fieres, J., Meier, K. and Schemmel, J. | A convolutional neural network tolerant of synaptic faults for low-power analog hardware | Proceedings of 2nd IAPR International Workshop on ArtificialNeural Networks in Pattern Recognition (ANNPR 2006), Lecture Notes in Artificial Intelligence 4087, 122-132, Springer (2006) | abstract, fulltext |
| Kaplan et al. 2009 | Kaplan, B., Bruederle, D., Schemmel, J. and Meier, K. | High-Conductance States on a Neuromorphic Hardware System | Proceedings of the 2009 International Joint Conference on Neural Networks, Atlanta, USA (2009): 2593-2599 | abstract, fulltext |
| Phillipp et al. 2007 | Philipp, S., Gruebl, A., Meier, K. and Schemmel, J. | Interconnecting VLSI Spiking Neural Networks Using Isochronous Connections | Proceedings of the International Work-Conference on Artificial Neural Networks (IWANN) 2007, LNCS 4507, p. 471-478, Springer | abstract |
| Schemmel 2009 | Schemmel, J. | VLSI Implementations of Very Large Scale Neuromorphic Circuits | talk on the ESSCIRC/BIECS 09, Athens, Greek | fulltext |
| Schemmel et al. 2006 | Schemmel, J., Gruebl, A., Meier, K. and Mueller, E. | Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model | Proceedings of the 2006 International Joint Conference on Neural Networks (IJCNN'06), 2006, IEEE Press | abstract, fulltext |
| Schemmel et al. 2007 | Schemmel, J., Bruederle, D., Meier, K., Ostendorf, B. | Modeling Synaptic Plasticity within Networks of Highly Accelerated I&F Neurons | Proceedings of the 2007 IEEE International Symposium on Circuits and Systems (2007) | abstract |
| Schemmel et al. 2010 | Schemmel, J., Brüderle, D., Grübl, A., Hock, M., Meier, K. and Millner, S. | A Wafer-Scale Neuromorphic Hardware System for Large-Scale Neural Modeling | Proceedings of the 2010 IEEE International Symposium on Circuits and Systems, Paris, France (2010):1947-1950 | fulltext |
