WP6: Neural hardware at the cell level

The objectives of this work package are the design and exploitation of a simulation platform based on VLSI circuits that simulate the activity of adaptive neural networks, using conductance-based models (Hodgkin-Huxley formalism).

The research group 'Engineering of neuromorphic systems' at ENSEIRB/University Bordeaux 1 is in charge of designing successive generations of custom VLSi circuits[1]


) and associated simulation platforms of spiking neural networks. The ASICs circuits compute in biological real-time the activity of neural elements using a complex conductance-based model (Hodgkin-Huxley formalism). The models parameters describe cortical neurons with diverse spiking/bursting activities. The ASICs are integrated on a simulation platform, where they can be organized as a neural network with an adaptive all-to-all connectivity. The platform is optimized to run in real-time temporal plasticity algorithms such as STDP (Spike-Timing Dependent Plasticity) or other Hebbian rules. The platform is used in FACETS as an efficient (computation speed, integration) tool for the exploration of the cortical cells models and plasticity algorithm in small networks.

Figure 1: Architecture and data flow in the simulation platform.
Image:Public--WP6_public_1stYear_Galway.png« Galway » : a BiCMOS full-custon ASIC (AMS 0.25microns process). Area: 10,5 mm2. 50k instances. 105 pads.

« Galway » functions :

  • Analog : 42 ionic and synaptic conductances (max 5 membranes/neurons)
  • Memory cells: 204 analog dynamic cells to store the conductances models parameters
  • Digital: Topology (conductances organisation) and parameters storage control
Figure 2: Microphotograph and description of the “Galway” ASIC. “Galway” computes 3 to 5-conductances neurons with programmable parameters, and is the core of a SNN simulation platform (see figure 1).

Figure 3: Electrical activity

(α) measured on an artificial neuron on ASIC configured to model a 5-conductances model (Na, K, Ca, K(Ca), leak)
(β) Stimulation current to trigger the bursting pattern.

Figure 4: Demonstration of the platform performances

Left: A 6-neurons network of RS (regular spiking) cortical neurons. All-to-all adaptative synaptic connections with STDP. All neurons receive correlated Poisson noise inputs.
Right: Evolution of the synaptic weights over time. The experiment simulates 60s of the network activity in real-time.
  1. VLSI = Very Large Scale integrated circuits
  2. ASIC=Application Specific Integrated Circuit = a custom made digital chip


19 Feb 2010